1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to an improvement of characteristic of a gate insulating film of a MIS (Metal-Insulator-Semiconductor) type semiconductor device.
2. Description of the Background Art
In a semiconductor integrated circuit device, a MIS type field effect transistor (MIS FET) is one of the important components. A MOS FET is a kind of MIS type FET, which employs an oxide film as an insulator. FIG. 12A is a sectional structure view showing a sectional structure of a conventional typical MOS FET. The MOS FET includes a pair of source/drain regions 3, 3, a gate oxide film 4 and a gate electrode 5. The MOS FET is formed in a region surrounded by a field oxide film 2 on a p type silicon substrate.
For the requirements of miniaturizing semiconductor device structures, in the MOS FET, the gate length is reduced. Furthermore, it is required to reduce a film thickness of gate oxide film 4. Gate oxide film 4 is made thinner in order to restrain the short channel effect caused by reducing the gate length. If the gate length is 0.3 .mu.m, for example, it is needed to implement gate oxide film 4 with a film thickness of 100 .ANG. or less. Thinning gate oxide film 4 caused the following problems.
FIG. 12B is an enlarged view of a gate region of a MOS transistor. A conventional gate oxide film 4 is formed by thermally oxidizing a main surface of silicon substrate 1.
Usually, a native oxide film 40 having a surface roughness of approximately 20 .ANG. is formed on the main surface of silicon substrate 1. Accordingly, when a gate oxide film 4 is formed by thermally oxidizing the surface of silicon substrate 1 on which the native oxide film 40 is formed, a portion "A" with a large film thickness and a portion "B" with a small thickness are formed in gate oxide film 4. The film thickness of gate oxide film 4 is smaller on a convex portion of the native oxide film 40 and the film thickness of gate oxide film 4 is larger on a concave portion of the native oxide film 40. Accordingly, gate oxide film 4 is formed having uneven film thickness, in which the breakdown voltage is reduced in a portion with a small film thickness. As described above, if gate oxide film 4 with a film thickness of 100 .ANG. or less is to be formed, the breakdown voltage of the gate oxide film further decreases because the effect of the surface roughness of the native oxide film 40 relatively increases. A certain experiment shows that, when an oxide film of an average film thickness of 100 .ANG. is formed, the film thickness of the oxide film formed in a corner portion in a lower layer is reduced to 40 .ANG..
Accordingly, a MOS transistor having a gate oxide film of the film thickness of 100 .ANG. or less has a disadvantage that it cannot use a thermal oxide film as a gate oxide film.
Also, problems similar to that described above are caused in other MOS devices. For example, a conventional PSD (Polysilicon Source and Drain) transistor will be described. A PSD transistor described below is disclosed in Japanese Patent Laying Open No. 61-16573, for example. FIG. 13G is a sectional structural view of a PSD transistor. Referring to FIG. 13G, a thick field oxide film 2 for element isolation is formed in a given region of a main surface of a p type silicon substrate 1. A pair of n type impurity regions 3, 3 are formed at intervals of a given distance in the main surface region of the p type silicon substrate 1 surrounded by field oxide film 2. Respective source/drain electrode layers 6, 6 formed of polycrystal silicon having conductivity are connected to the surface of the pair of n type impurity regions 3, 3, respectively. The source/drain electrode layers 6, 6 extend on the field oxide film 2. The main surface region of the p type silicon substrate 1 disposed between the pair of n type impurity regions 3, 3 constitutes a channel region 10 of the transistor. Relatively thin gate insulating films 4a, 4b are formed on the surface of the channel region 10. Furthermore, a gate electrode 5 formed of polysilicon provided with conductivity is formed on the surface of the gate insulating films 4a, 4b. The gate electrode 5 is insulated and isolated from the source/drain electrode layers 6 by the gate insulating films 4b. Furthermore, a part of the gate electrode 5 extends above these source/drain electrode layers 6, 6. The surface of the PSD transistor is covered with a thick interlayer insulating layer 7. Contact holes 8 which reach the source/drain electrode layers 6, 6 are formed in the interlayer insulating layer 7. Interconnection layers 9 are connected to the source/drain electrode layers 6, 6 through the contact holes 8.
A feature of this PSD transistor structure is that the n type impurity regions 3, 3 are formed in a self-aligning manner with respect to the source/drain electrode layers 6, 6, and that a part of the gate electrode 5 extends above the source/drain electrode layers 6, 6.
Next, the process of manufacturing the PSD transistor will be described. FIGS. 13A-13G are manufacturing process sectional views illustrating the process of manufacturing a PDS transistor. First, referring to FIG. 13A, a thick field oxide film 2 is formed in a given region on a main surface of a p type silicon substrate 1 using the LOCOS (Local Oxidation of Silicon ) method. Next, a polysilicon layer 6 is deposited on the main surface of the p type silicon substrate 1 and impurity ions are implanted for providing it with conductivity. On the surface of polysilicon layer 6, undulation on the order of 500 .ANG. is formed.
Next, as shown in FIG. 13B, a silicon oxide film 11 is deposited on the surface of the polysilicon layer 6 by the chemical vapor deposition (CVD) method.
Furthermore, referring to FIG. 13C, a portion of the silicon oxide film 11 and the polysilicon layer 6 in which a gate is to be formed is selectively removed by plasma dry etching method to form an opening portion 12. The surface of the p type silicon substrate 1 is exposed in the opening portion 12.
Next, referring to FIG. 13D, it is heat-treated in an oxidizing atmosphere to form silicon oxide films 4a, 4b on the exposed surface of the p type silicon substrate 1 in the opening portion 12 and on the side surfaces of the polysilicon layers 6 facing the opening portion 12. Subsequently, performing thermal treatment in a nitriding atmosphere, the impurity introduced into the polysilicon layer 6 is diffused into the p type silicon substrate 1. Thus, n type impurity regions 3, 3 are formed.
Furthermore, referring to FIG. 13E, a doped polysilicon layer 5 is deposited on the surface of the insulating layer 11 and the gate insulating layers 4a, 4b.
Furthermore, referring to FIG. 13F, the polysilicon layer 5 and the insulating layer 11 are patterned into given form using the lithography method and the etching method to form a gate electrode 5 and an insulating layer 11b.
Subsequently, referring to 13G, after forming a thick interlayer insulating layer 7, contact holes 8 which reach the source/drain electrode layers 6, 6 are formed. Next, aluminum interconnection layers 9 are formed connected to the source/drain regions 6 through the contact holes 8. In the above process, a PSD transistor is manufactured.
A problem with the PSD transistor manufactured by the above described method is that the thickness of the gate insulating film 4a is not uniform. The non-uniformity of film 4A degrades the gate breakdown voltage. A description thereof will be made below. FIG. 14 is a partial sectional structure drawing including the channel region 10 in the step shown in FIG. 13B. The surface of the polysilicon layer 6 becomes rough corresponding to the shape of the grains. Also, the surface condition of the insulating layer 11 formed on the polysilicon layer 6 surface similarly becomes rough reflecting the surface shape of the polysilicon layer 6.
Next, FIG. 15 is an enlarged sectional view of an opening portion 12 formed as shown in FIG. 13C. As the insulating layer 11 having a rough surface shape and the polysilicon layer 6 are etched and removed away, the channel region 10 surface of the p type silicon substrate 1 surface is also formed as an uneven plane with large undulation reflecting this surface shape. Specifically, this is because the surface of the silicon substrate 1 is also continually etched, since the polysilicon layer 6 and the silicon substrate 1 have no etching selectivity.
FIG. 16 is a partial enlarged view of the channel of the PSD transistor provided with the gate insulating films 4a, 4b by the step shown in FIG. 13D. When a silicon oxide film is formed by the thermal oxidation method on the surface of the channel region 10 having a rough surface shape, the thickness of the silicon oxide film becomes thin at a sharp convex portion, and edge dislocation is produced in extreme cases. Accordingly, for the entire gate insulating layer 4a, the thickness becomes uneven. Thus, the gate dielectric breakdown voltage is degraded where the film is thin, so that the gate dielectric breakdown voltage is degraded for the entire gate oxide film 4a. Such problems are serious in a range of a film thickness of gate insulating film 4a of less than about 200 .ANG..
As described above, in a conventional MIS transistor, an insulating layer formed by thermal oxidation is less suitable as a gate insulating layer of a transistor as a gate insulating layer becomes thinner.